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24C01C
1K 5.0V I2CTM Serial EEPROM
Features:
* Single Supply with Operation from 4.5V to 5.5V * Low-Power CMOS Technology: - Read current 1 mA, max. - Standby current 5 A, max. * 2-Wire Serial Interface, I2CTM Compatible * Cascadable up to Eight Devices * Schmitt Trigger Inputs for Noise Suppression * Output Slope Control to Eliminate Ground Bounce * 100 kHz and 400 kHz Clock Compatibility * Page Write Time 1 ms max. * Self-Timed Erase/Write Cycle * 16-Byte Page Write Buffer * ESD Protection >4000V * More than 1 Million Erase/Write Cycles * Data Retention >200 Years * Factory Programming Available * Packages include 8-lead PDIP, SOIC, TSSOP, DFN, TDFN and MSOP * Pb-Free and RoHS Compliant * Temperature Ranges: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C
Description:
The Microchip Technology Inc. 24C01C is a 1K bit Serial Electrically Erasable PROM with a voltage range of 4.5V to 5.5V. The device is organized as a single block of 128 x 8-bit memory with a 2-wire serial interface. Low-current design permits operation with max. standby and active currents of only 5 A and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data and has fast write cycle times of only 1 ms for both byte and page writes. Functional address lines allow the connection of up to eight 24C01C devices on the same bus for up to 8K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (3.90 mm), 8-pin 2x3 DFN and TDFN, 8-pin MSOP and TSSOP packages.
Block Diagram
A0 A1 A2 HV Generator Memory Control Logic
I/O Control Logic
XDEC
EEPROM Array
SDA SCL VCC VSS Sense Amp. R/W Control YDEC
Package Types
PDIP, MSOP
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC Test SCL SDA A0 A1 A2 VSS
SOIC, TSSOP
1 2 3 4 8 7 6 5 VCC Test SCL SDA
DFN/TDFN
A0 1 A1 2 A2 3 VSS 4 8 VCC 7 Test 6 SCL 5 SDA
(c) 2008 Microchip Technology Inc.
DS21201J-page 1
24C01C
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-40C to +125C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = +4.5V to 5.5V Automotive (E): VCC = +4.5V to 5.5V Min. -- 0.7 VCC -- 0.05 VCC Max. -- -- 0.3 VCC -- Units -- V V V -- -- -- (Note) TA = -40C to +85C TA = -40C to +125C Conditions
DC CHARACTERISTICS Param. No. D1 D2 D3 D4
Sym. -- VIH VIL VHYS
Characteristic A0, A1, A2, SCL, SDA and WP pins: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs)
D5 D6 D7 D8 D9 D10 Note:
VOL ILI ILO CIN, COUT ICC Write ICCS
-- -- -- -- -- -- --
0.40 1 1 10 1 3 5
V A A pF mA mA A
IOL = 3.0 mA @ VCC = 4.5V VIN = VSS or VCC, WP = VSS VOUT = VSS or VCC VCC = 5.0V (Note) TA = 25C, f = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V VCC = 5.5V, SDA = SCL = VCC WP = VSS
ICC Read Operating current Standby current
This parameter is periodically sampled and not 100% tested.
DS21201J-page 2
(c) 2008 Microchip Technology Inc.
24C01C
TABLE 1-2: AC CHARACTERISTICS
Electrical Characteristics: Industrial (I): VCC = +4.5V to 5.5V Automotive (E): VCC = +4.5V to 5.5V Characteristic Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time (Note 1) Min. -- -- 4000 600 4700 1300 -- -- -- 4000 600 4700 600 0 250 100 4000 600 -- -- 4700 1300 10 + 0.1CB Max. 100 400 -- -- -- -- 1000 300 300 -- -- -- -- -- -- -- -- -- 3500 900 -- -- 250 Units kHz ns ns ns ns ns ns ns ns ns ns ns -- (I-temp) -- (I-temp) -- (I-temp) -- (I-temp) -- -- (I-temp) -- (I-temp) (Note 2) -- (I-temp) -- (I-temp) -- (I-temp) -- (I-temp) (Note 1) TA = -40C to +85C TA = -40C to +125C Conditions AC CHARACTERISTICS Param. No. 1 2 3 4 5 6 7 8 9 10 11 12
Sym. FCLK THIGH TLOW TR TF
THD:STA Start condition hold time TSU:STA Start condition setup time THD:DAT Data input hold time TSU:DAT Data input setup time TSU:STO Stop condition setup time TAA TBUF Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum CB 100 pF Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance
13
TOF
ns
14 15 16 Note 1: 2: 3: 4:
TSP TWC --
-- -- 1,000,000
50 1.5 1 --
ns ms
(Note 3) -- (I-temp)
cycles 25C (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model, which can be obtained from Microchip's web site at www.microchip.com.
(c) 2008 Microchip Technology Inc.
DS21201J-page 3
24C01C
FIGURE 1-1: BUS TIMING DATA
5
2
D4
4
SCL SDA IN
7 6 14
3
8
9
10
11 SDA OUT
12
DS21201J-page 4
(c) 2008 Microchip Technology Inc.
24C01C
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name A0 A1 A2 VSS SDA SCL Test VCC
PIN FUNCTION TABLE
8-pin PDIP 1 2 3 4 5 6 7 8 8-pin SOIC 1 2 3 4 5 6 7 8 8-pin TSSOP 1 2 3 4 5 6 7 8 8-pin MSOP 1 2 3 4 5 6 7 8 8-pin DFN/TDFN 1 2 3 4 5 6 7 8 Chip Select Chip Select Chip Select Ground Serial Data Serial Clock Test +4.5V to 5.5V Power Supply Function
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal; therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24C01C devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS.
2.4
Test
This pin is utilized for testing purposes only. It may be tied high, tied low or left floating.
2.5
Noise Protection
The 24C01C employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 3.8 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus.
(c) 2008 Microchip Technology Inc.
DS21201J-page 5
24C01C
3.0 FUNCTIONAL DESCRIPTION
4.4 Data Valid (D)
The 24C01C supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device that generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions, while the 24C01C works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in firstout fashion.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1).
4.5
Acknowledge
Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. Note: The 24C01C does not generate any Acknowledge bits if an internal programming cycle is in progress.
4.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2)
A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.
DS21201J-page 6
(c) 2008 Microchip Technology Inc.
24C01C
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
(A)
(B)
(C)
(D)
(C)
(A)
SDA
Start Condition
Address or Acknowledge Valid
Data Allowed to Change
Stop Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
(c) 2008 Microchip Technology Inc.
DS21201J-page 7
24C01C
5.0 DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a four-bit control code; for the 24C01C this is set as `1010' binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24C01C devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a `1' a read operation is selected, and when set to a `0' a write operation is selected. Following the Start condition, the 24C01C monitors the SDA bus checking the control byte being transmitted. Upon receiving a `1010' code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C01C will select a read or write operation.
CONTROL BYTE FORMAT
Read/Write Bit Chip Select Bits 0 A2 A1 A0 R/W ACK
Control Code S 1 0 1
Slave Address Start Bit Acknowledge Bit
5.1
Contiguous Addressing Across Multiple Devices
The Chip Select bits A2, A1, A0 can be used to expand the contiguous address space for up to 8K bits by adding up to eight 24C01C devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9, and A2 as address bit A10. It is not possible to write or read across device boundaries.
DS21201J-page 8
(c) 2008 Microchip Technology Inc.
24C01C
6.0
6.1
WRITE OPERATIONS
Byte Write
Following the Start signal from the master, the device code (4 bits), the Chip Select bits (3 bits), and the R/W bit, which is a logic low, is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24C01C. After receiving another Acknowledge signal from the 24C01C the master device will transmit the data word to be written into the addressed memory location. The 24C01C acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24C01C will not generate Acknowledge signals (Figure 6-1).
After the receipt of each word, the four lower order Address Pointer bits are internally incremented by one. The higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 6-2).
Note:
6.2
Page Write
The write control byte, word address and the first data byte are transmitted to the 24C01C in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 15 additional data bytes to the 24C01C which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a Stop condition.
Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
FIGURE 6-1:
Bus Activity Master SDA Line Bus Activity S T A R T S
BYTE WRITE
Control Byte Word Address Data S T O P P A C K A C K A C K
FIGURE 6-2:
Bus Activity Master S T A R T S
PAGE WRITE
Control Byte Word Address (n) S T O P P A C K A C K A C K A C K A C K
Data n
Data n +1
Data n + 15
SDA Line Bus Activity
(c) 2008 Microchip Technology Inc.
DS21201J-page 9
24C01C
7.0 ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for flow diagram.
ACKNOWLEDGE POLLING FLOW
Send Write Command
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? YES Next Operation
NO
DS21201J-page 10
(c) 2008 Microchip Technology Inc.
24C01C
8.0 READ OPERATION
8.2 Random Read
Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read and sequential read. Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C01C as part of a write operation. After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C01C will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24C01C discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read.
8.1
Current Address Read
The 24C01C contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24C01C issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24C01C discontinues transmission (Figure 8-1).
FIGURE 8-1:
S T A R T S
CURRENT ADDRESS READ
Control Byte S T O P P A C K N O A C K
8.3
Sequential Read
Bus Activity Master SDA Line Bus Activity
Data
Sequential reads are initiated in the same way as a random read except that after the 24C01C transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24C01C to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24C01C contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 7F to address 00.
FIGURE 8-2:
RANDOM READ
S T A R T S Control Byte Word Address (n) S T A R T S A C K A C K A C K N O A C K Control Byte Data (n) S T O P P
Bus Activity Master
SDA Line Bus Activity
FIGURE 8-3:
Bus Activity Master SDA Line
SEQUENTIAL READ
Control Byte Data n Data n + 1 Data n + 2 Data n + X S T O P P A C K A C K A C K A C K N O A C K
Bus Activity
(c) 2008 Microchip Technology Inc.
DS21201J-page 11
24C01C
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX T/XXXNNN YYWW
Example:
24C01C I/P e3 13F 0527
8-Lead SOIC (3.90 mm)
XXXXXXXT XXXXYYWW NNN
Example:
24C01CI SN e3 0527 13F
8-Lead TSSOP
XXXX TYWW NNN
Example:
4C1C I527 13F
8-Lead MSOP
Example:
XXXXT YWWNNN
4C1CI 52713F
8-Lead 2x3 DFN
XXX YWW NN
Example:
2N7 527 13
8-Lead 2x3 TDFN
XXX YWW NN
Example:
AN7 527 13
DS21201J-page 12
(c) 2008 Microchip Technology Inc.
24C01C
1st Line Marking Codes Part Number TSSOP 24C01C Note: 4C1C T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) MSOP I Temp. 4C1CT 2N7 E Temp. 2N8 I Temp. AN7 E Temp. AN8 DFN TDFN
e3
Note:
For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
Note:
Note:
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
(c) 2008 Microchip Technology Inc.
DS21201J-page 13
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DS21201J-page 22
(c) 2008 Microchip Technology Inc.
24C01C
APPENDIX A:
Revision D
Corrections to Section 1.0, Electrical Characteristics.
REVISION HISTORY
Revision E
Added DFN package.
Revision F (01/2007)
Revised Features Section; Deleted Commercial Temp; Replaced Package Drawings; Replaced On-Line Support page; Revised Product ID System.
Revision G (03/2007)
Replaced Package Drawings (Rev. AM).
Revision H (04/2008)
Replaced Package Drawings; Added TDFN package; Revised Product ID section.
Revision J (08/2008)
Updated Features Section; Added Table 2-1 Pin Function Table; Corrections to Table 1-1, DC Characteristics; Updated Table 1-2, AC Characteristics; Updated Package Drawings.
(c) 2008 Microchip Technology Inc.
DS21201J-page 23
24C01C
NOTES:
DS21201J-page 24
(c) 2008 Microchip Technology Inc.
24C01C
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2008 Microchip Technology Inc.
DS21201J-page 25
24C01C
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: 24C01C Questions: 1. What are the best features of this document? Y N Literature Number: DS21201J FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21201J-page 26
(c) 2008 Microchip Technology Inc.
24C01C
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b)
Device: 24C01C: 1K I2C Serial EEPROM 24C01CT: 1K I2C Serial EEPROM (Tape and Reel)
c)
24C01C-I/P: Industrial Temperature, PDIP Package 24C01C-E/SN: Extended Temperature, SOIC Package 24C01C-I/MNY: Industrial Temperature, 2x3 TDFN Package
Temperature Range:
I E
= -40C to +85C = -40C to +125C
Package:
Plastic DIP (300 mil Body), 8-lead Plastic SOIC, (3.90 mm Body), 8-lead TSSOP (4.4 mm Body), 8-lead Plastic Micro Small Outline (MSOP), 8-lead Plastice Dual Flat (DFN), No lead, 2x3 mm body, 8-lead MNY(1) = Plastic Dual Flat (TDFN), No lead package, 2x3 mm body, 8-lead
P SN ST MS MC
= = = = =
Note 1: "Y" indicates a Nickel, Palladium, Gold (NiPdAu) finish.
(c) 2008 Microchip Technology Inc.
DS21201J-page 27
24C01C
NOTES:
DS21201J-page 28
(c) 2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2008 Microchip Technology Inc.
DS21201J-page 29
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS21201J-page 30
(c) 2008 Microchip Technology Inc.

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